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Embedded Imaging Processing Algorithm Evaluation and Development Board:

Dual processors, Xilinx Virtax-5 sx95t FPGA and TI TMS648 DSP (up to 900MHz) with 64MB DDR2 Memory,

85MHz Camera Links Digital Video Inputs/Output, two inputs and one output,

Analog Video Inputs/Outputs, one PAL/NTSC video input/output, one HDTV input/output, One XVGA,

Communication Ports, two RS232 serial ports, JTAG ports, external digital outputs, LEDs

Printed Circuit Boards, 17-layers with impedance balanced traces,

MEMS Gyro Iterface Port, one external port for Analog Device MEMS Gyro interface,

Compact Size, 4" x 5", 5VDC Power Input, 2A with process running.

Software (option):

Laplacian-Gaussian Pyramid Algorithm, real-time 5 Level 800x800 pixels 8-bit depth

Affine image warping algorithm, real-time 800x800 pixels 8-bit full image warping with linear interpolation,